High density interconnect (HDI) substrates are growing in market demand, driven by the increase in number of I/O ports and decrease in the size of devices with increased functionality and higher speeds. Tape substrates have several typical advantages over rigid substrates, including:
1) Finer line width/space with higher circuit density
2) Thin in profile and light in weight
3) Better thermal performance
With the number of I/O ports constantly increasing, flip chip is a key technology which provides benefits such as high I/O, finer pitch interconnection, and superior electrical and thermal performance, which drive its applications across specific segments. There is a continuous demand for fine pitch interconnection including display drivers, CMOS image sensors, baseband processors, power management units, and so on.
Low-cost and high reliability interconnection processes will play a key role in the development of advanced packaging for the next century. Diffusion bonding is a method of joining metallic or non-metallic materials. This bonding technique is based on the atomic diffusion of elements at the joining interface. In the technology of diffusion bonding to connect IC/Chip to the substrate, a combination of heat and pressure is applied across a contact interface having as one portion a deformable layer so that under pressure the plastic deformation of that layer operates to bring the interface to the bonding temperature more quickly and to enhance diffusion. The result is that strong and reliable bonds are formed. However, when the bond pitch is reduced to where the contact is 10 μm wide and the spacing between contacts is 10 μm (microns) or below, a number of independent aspects require consideration. Copper, as conductor, is usually preferred due to its excellent electrical and thermal conductivity. The deformable layer must provide the requisite electrical properties. The deformable layer must deform at an essentially uniform pressure from contact to contact and there must be enough top width on the bonding surface of the trace so that a full contact interface and a proper surface on the deformable layer is formed. As the bond pitch becomes tighter and tighter, the traditional semi-additive and subtractive methods have limitations for reducing the trace pitch to below 20 μm based on the current reel to reel manufacturing capabilities; specifically, it is difficult to maintain the top and bottom trace ratio as 1. In general, the diffusion rate, in term of diffusion coefficient D, is defined as D=Do exp(−Q/RT), where Do is the frequency factor depending on the type of lattice and the oscillation frequency of the diffusing atom, Q is the activation energy, R is the gas constant and T is the temperature in Kelvin.
Diffusion of atoms is a thermodynamic process where temperature and diffusibility of the material are critical parameters. Creep mechanism allows a material flow to produce full intimate contact at the joint interface as required for diffusion bonding. Therefore, the surface finish of the trace and the selection of bonding temperature and loading are important factors in the diffusion bonding process. Other factors such as plastic deformation, thermal conductivity, thermal expansion, and bonding environment also effect the bonding process, particularly at high bonding temperatures.
Thermo-compression bonding has a predicted application in flip chip assembly using gold bumps. The bumps are made on substrates using stud bumping methods or electrolytic gold plating. During the process of bonding, the chip is picked up and aligned face down to bumps on a heated substrate. When the bonding component presses down, the gold bumps deform and make intense contact with the pads of bonding causing pure metal to metal welding to take place. Thermal compression bonding needs a flip chip bonder that is capable of generating a greater bonding temperature of 300° Celsius with a force of around 100N/bump and a greater extent of parallelism between substrate and chip. For greater yield bonding, the temperature and bonding force are required to be well-controlled. In order to avoid damaging the semiconductor material, the bonding force must be graduated. Excessive bonding force may cause cracks in the passivation of the chip and sometimes bridging of the bumps in a fine pitch array due to over-deformation of the bumps. The selection of surface finish on the trace is critical to improve the diffusion bonding process.
U.S. Pat. No. 8,940,581 (Lee et al), U.S. Pat. No. 8,967,452 (Cheung et al), U.S. Pat. No. 8,440,506 (Roberts et al), U.S. Pat. No. 9,153,551 (Liang et al), and U.S. Pat. No. 7,878,385 (Kumar et al) disclose thermal compression processes.